What is the purpose of WFI and WFE instructions and the event signals ?

We have 2 instructions for entering low-power standby state where most clocks are gated: WFI and 
WFE.

They differ slightly in their entry and wake-up conditions, with the main difference being that 
WFE makes use of the event register, the SEV instruction and EVENTI, EVENTO signals.

WFI is targeted at entering either standby, dormant or shutdown mode, where an interrupt is 
required to wake-up the processor.

A usage for WFE is to put it into a spinlock loop. Where a CPU wants to access a shared resource 
such as shared memory, we can use a semaphore flag location managed by exclusive load and store 
access. If multiple CPUs are trying to access the resource, one will get access and will start to 
use the resource while the other CPUs will be stuck in the spinlock loop. To save power, you can 
insert the WFE instruction into the loop so the CPUs instead of looping continuously will enter 
STANDBTWFE. Then the CPU who has been using the resource should execute SEV instruction after it 
has finished using the resource. This will wake up all other CPUs from STANDBYWFE and another CPU 
can then access the shared resource.

The reason for having EVENTI and EVENTO is to export a pulse on EVENTO when an SEV instruction is 
executed by any of the CPUs. This signal would connect to EVENTI of a second Cortex-A5 MPCore 
cluster and would cause any CPUs in STANDBYWFE state to leave standby. So these signals just 
expand the usage of WFE mode across multiple clusters. If you have a single cluster, then you do 
not need to use them.

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka15473.html

Address Space ID (ASID)

For EL0 and EL1, there are two translation tables. TTBR0_EL1 provides translations for the bottom of Virtual Address space, which is typically application space and TTBR1_EL1 covers the top of Virtual Address space, typically kernel space. This split means that the OS mappings do not have to be replicated in the translation tables of each task.

Translation table entries contain a non-global (nG) bit. If the nG bit is set for a particular page, it is associated with a specific task or application. If the bit is marked as 0, then the entry is global and applies to all tasks.

For non-global entries, when the TLB is updated and the entry is marked as non-global, a value is stored in the TLB entry in addition to the normal translation information. This value is called the Address Space ID (ASID), which is a number assigned by the OS to each individual task. Subsequent TLB look-ups only match on that entry if the current ASID matches with the ASID that is stored in the entry. This permits multiple valid TLB entries to be present for a particular page marked as non-global, but with different ASID values. In other words, we do not necessarily need to flush the TLBs when we context switch.

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0024a/CDDEIJCH.html

-mcpu/--with-cpu, -mfpu/--with-fpu, -mfloat-abi/--with-float are,

generally, orthogonal options:

 -mcpu/--with-cpu selects the integer side instruction set available.

 -mfpu/--with-fpu selects the FP/Advanced SIMD/WMMX instruction set available.

 -mfloat-abi/--with-float selects how floating-point instructions may be used.

The manual gives full details, but in summary:

 * -mfloat-abi=soft means don't use any Floating-Point instructions

anywhere, simulate them with integer side instructions.

 * -mfloat-abi=softfp means you can use FP instructions, but still use

the standard calling convention which passes float/double arguments in

integer registers.

 * -mfloat-abi=hard means you can use FP instructions, and the calling

convention changes to pass float/double arguments in S/D registers.

Thanks,

Matt

Ubuntu 11.10 에서 ICS 빌드에러 수정

https://groups.google.com/d/topic/android-building/AgeruY7XIwQ/discussion